Electronics demand more integrated circuits in an integrated circuit package while paradoxically providing less physical space in the system for the increased integrated circuits content. Some technologies primarily focus on integrating more functions into each integrated circuit. Other technologies focus on stacking these integrated circuits into a single package. While these approaches provide more functions within an integrated circuit, they do not fully address the requirements for lower height, smaller space, and cost reduction.
Modern electronics, such as smart phones, personal digital assistants, location based services devices, servers, and storage arrays, are packing more integrated circuits into an ever-shrinking physical space with expectations for decreasing cost. Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new package technologies while others focus on improving the existing package technologies. Research and development in the existing package technologies may take a myriad of different directions.
Numerous package approaches stack multiple integrated circuit dice or package in package (PIP) or a combination thereof. The electrical connections to the each of the stacked integrated circuit require an increased amount of space from by spacers, such as silicon or interposers, or by the space required for the electrical connections, such as wire loops for bond wires.
Current spacers require additional steps and structures increasing manufacturing costs and decreasing manufacturing yields. These spacers also limit the amount of height reduction. Space required for the different electrical connection types limit the overall size, e.g. height, width, and length, of the package. Other spacers, such as spacer films, offer potentially thinner spacing structures but do not provide sufficient rigidity or uniform thickness. These problems may result in tilting or non-uniform spacing between the stacked integrated circuits.
In addition, multi-chip packages, whether vertically or horizontally arranged, can also present problems because they usually must be assembled before the component chips and chip connections can be tested. The electrical bond pads on a die are so small, it is difficult to test die before assembly onto a substrate. Thus, when die are mounted and connected individually, the die and connections can be tested individually, and only known-good-die or known-good-device (“KGD”), free of defects, are then assembled into larger circuits. A fabrication process that uses KGD is therefore more reliable and less prone to assembly defects introduced due to bad die or bad devices.
For example, two of the common integrated circuit die stacking methods are: (a) larger lower die combined with a smaller upper die, and (b) so-called same-size die stacking. With the former, the die can be very close vertically since the electrical bond pads on the perimeter of the lower die extend beyond the edges of the smaller die on top. With same-size die stacking, the upper and lower dice are spaced more vertically apart to provide sufficient clearance for the bond wires to the lower die. As discussed, both these methods have inherent KGD and assembly process yield loss disadvantages since KGD cannot be used for fabricating these configurations.
Another example is package level stacking. This concept includes stacking of two or more packages. KGD and assembly process yields are not an issue since each package can be tested prior to assembly, allowing KGD to be used in assembling the stack. But package level stacking can pose other problems. One problem is package-to-package assembly process difficulties caused by irregularities in the flatness or co-planarity of the lower package. Another problem results from the increased stiffness of the overall assembly, which can lead to reduced board level reliability. Still another problem can arise from poor heat dissipation from the upper package.
Thus, a need still remains for a stacked integrated circuit package system providing low cost manufacturing, improved yield, and thinner height for the integrated circuits. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.